1. Field of the Invention
This invention relates to a signal processing device which is arranged to process an information signal.
2. Description of the Related Art
An electronic still video system has been known as one of the information signal processing devices.
The electronic still video system is arranged as follows: a luminance component of a color still image signal is frequency-modulated. Two color-difference signals which are included in the color still image signal as a chrominance component are frequency-modulated after they are processed into a color-difference line-sequential signal. The frequency-modulated luminance signal and the frequency-modulated color-difference line-sequential signal thus obtained are frequency-multiplexed into a recording image signal to be recorded on a magnetic disc. The recording image signal recorded on the magnetic disc is reproduced. From the reproduced signal, the frequency-modulated luminance signal and the frequency-modulated color-difference line-sequential signal are separated. These separated signals are frequency-demodulated. After frequency demodulation, the color-difference line-sequential signal is restored to the two color-difference signals by converting the line-sequential state into a coincident state. The two color-difference signals are further converted into a chrominance signal by quadrature two-phase modulation. The chrominance signal thus obtained is frequency-multiplexed with the frequency-demodulated luminance signal to obtain and output a TV signal from the electronic still video system.
FIG. 1 of the accompanying drawings shows in outline and in part the arrangement of a signal processing circuit included in the reproducing apparatus of the above-stated electronic still video system. The circuit shown in FIG. 1 represents a chrominance color encoder which is arranged to convert the two kinds of color-difference signals into a chrominance signal by using balanced modulators.
Referring to FIG. 1, a color-difference signal R-Y is inputted to a clamp circuit 1 and a color-difference signal B-Y to a clamp circuit 3. These signals R-Y and B-Y are clamped for a period of time designated by clamp pulse signals CLP which are inputted respectively to the clamp circuits 1 and 3. After the clamping process, the signal R-Y is supplied to a balanced modulator 2 and the signal B-Y to a balanced modulator 4. A modulation carrier signal fsc1 is supplied to the balanced modulator 2 and a modulation carrier signal fsc2 to the balanced modulator 4. Each of these balanced modulators 2 and 4 is arranged to perform a balanced modulating process on the signal R-Y or the signal B-Y with the modulation carrier signal fsc1 or fsc2. The outputs of the balanced modulators 2 and 4 are supplied to an adder 5.
In cases where the modulation carrier signals fsc1 and fsc2 are arranged to conform to the TV signal of, for example, the NTSC color system, both the modulation carrier signals fsc1 and fsc2 are arranged to be at a frequency 3.58 MHz. The phase of the carrier signal fsc1 is then arranged to be at 90.degree. while that of the other carrier signal fsc2 is at 0.degree.. At the adder 5, a chrominance signal is formed by adding together the signals supplied from the balanced modulators 2 and 4. The chrominance signal thus formed is outputted from the adder 5.
FIG. 2 is a circuit diagram showing in part the circuit arrangement of the color encoder shown in FIG. 1. The circuit of FIG. 2 corresponds to the clamp circuit 1 and the balanced modulator 2 or to the clamp circuit 3 and the balanced modulator 4 shown in FIG. 1.
FIGS. 3(a) to 3(i) and 4(a) to 4(j) show, in timing charts, signal waveforms obtained from the various parts of the circuit shown in FIG. 2. The operation of the circuit shown in FIG. 2 is described below with reference to FIGS. 3(a) to 3(i) and 4(a) to 4(j):
Referring to FIG. 2, a clamp circuit is formed with transistors Q1 to Q5, resistors R2 to R4 and a capacitor C1. A clamp pulse signal CLP which is as shown at FIG. 4(i) is inputted to the base of the transistor Q5.
Assuming that a voltage obtained when the clamp pulse signal CLP is at a high level is "K1.multidot.Vcc+VBE" (wherein K1 represents a constant, Vcc a power supply voltage and VBE a voltage between the base and the emitter of the transistor Q5). For example, a constant current flows to an analog switch which consists of transistors Q1 and Q2 through a current mirror circuit which consists of transistors Q3 and Q4. The constant current is thus applied to the analog switch during the high-level period of the clamp pulse signal CLP. The DC potential of the color encoder is thus fixed at a bias potential V1.
In a case where horizontal synchronizing pulses are employed as the clamp pulse signal CLP, for example, a clamping action is performed to fix at above-stated bias potential V1 the blanking level of the color-difference signal which is inputted from a terminal VIN in a state as shown in FIG. 4(b).
The color-difference signal which has been subjected to the above-stated clamping action is supplied to the base of a transistor Q6 which forms a buffer circuit. The output of the transistor Q6 is inputted to a differential amplifier which consists of transistors Q8 and Q10. The output of the differential amplifier is inputted to the balanced modulator as two differential output signals.
A circuit which is composed of transistors Q31, Q12 and Q13 and resistors R26 and R11 is arranged to form another reference voltage input (a blanking level) for the differential amplifier. The base of the transistor 31 of this circuit is caused to be constantly in a saturated state by the resistor 26 and to have a saturation voltage between the collector and the emitter thereof. This is because the clamping analog switch which is formed by the transistors Q1 and Q2 is also in a saturated state like the transistor Q31 during the clamping process of the clamping analog switch, i.e., during the blanking period, and the base voltage of the transistor Q6 is not at the bias potential V1 and is higher than the bias voltage V1 by as much as the saturation voltages of the transistors Q1 and Q2. The constant saturated state of the base of the transistor Q31 is thus arranged to permit compensation for the higher portion of the base voltage of the transistor Q6. This compensation can be made by suitably adjusting the value of the resistor R26.
Assuming that a value "K2.multidot.Vcc+VBE" (wherein K2 represents a constant, Vcc the power supply voltage and VBE a voltage between the base and the emitter of the transistor to be connected) is expressed as V2 and that a resistor R5 is equal to a resistor R11, a resistor R7 is equal to a resistor R10 and a resistor R6 is equal to a resistor 9, differential signals obtained by compensating the color-difference signal are inputted to the transistors Q14 and Q18.
Meanwhile, the modulation carrier signal fsc which is as shown in FIG. 3(a) is inputted to the bases of transistors Q15, Q17, Q19 and Q21; and four kinds of signals which are balanced-modulated with the modulation carrier signal fsc and are as shown in FIGS. 3(c) to 3(f) are outputted from the collectors of the transistors Q15, Q17, Q19 and Q21, respectively. The voltage level of the modulation carrier signal fsc which is included in the signals shown in FIGS. 3(c) to 3(f) is determined by currents flowing to resistors R12, R13, R15 and R16. For example, the voltage level of the modulation carrier signal fsc is arranged to be set at about 0.2 V with the resistors R12, R13, R15 and R16 assumed to be of equal values.
Resistors R20 and R22 are arranged to be of equal values, and resistors R18 and R23 are arranged to be of equal valves. With these resistors thus arranged, transistors Q23 and Q25 become operative and transistors Q22 and Q26 inoperative during the high-level period of the modulation carrier signal fsc shown in FIG. 3(a). This is because the voltage level of the modulation carrier signal fsc included in the signals shown in FIGS. 3(c) to 3(f) are about 8 VT (VT=KT/q, wherein K represents a Boltzmann's constant; T the absolute temperature; and q the electric charge of electrons). Then, in each of the two pairs of transistors Q22 and Q23 and transistors Q25 and Q26, one transistor of the pair can be completely turned off.
At this time, the signal outputted from the collector of the transistor Q25 is outputted from an output terminal VO1 as shown in FIG. 2. The signal from the collector of the transistor Q23 is outputted from another output terminal VO2. This means that the outputs of a differential amplifier which is formed by the transistors Q23 and Q25 are outputted from the output terminals VO1 and VO2 of FIG. 2.
During the low-level period of the modulation carrier signal fsc which is as shown in FIG. 3(a), the transistors Q22 and Q26 are operative while the transistors Q23 and Q25 are inoperative. Then, the outputs of a differential amplifier, which is formed by the transistors Q22 and Q26, are outputted from the output terminals VO1 and VO2.
In a case where the differential color-difference signals which are inputted to the bases of the transistors Q14 and Q18 are balanced in terms of both direct and alternating currents, the balanced-modulated color-difference signals which are as shown in FIGS. 3(g) and 3(h) are not outputted from the output terminals VO1 and VO2 during a period of time A shown in FIGS. 3(a) to 3(i), that is, during the blanking period. The balanced-modulated color-difference signals are outputted from the output terminals VO1 and VO2 as shown in FIGS. 3(g) and 3(h) during a period of time B which is also shown in FIGS. 3(a) to 3(i), that is, during a period of having the color-difference components present.
However, a circuit arranged in the above-stated manner hardly performs a normal operation if the characteristics of each pair of elements are not matched to each other. For example, in a case where the circuit shown in FIG. 2 is arranged in the form of an integrated circuit, current density would be changed by unevenness of the areas of the emitters of the transistors resulting from deviations of mask pattern, etc. The change in current density then causes an error .DELTA.VBE of the voltage between the base and the emitter of each transistor.
The above-stated error .DELTA.VBE also arises if each pair of transistors have uneven characteristics among the transistors Q1 to Q13 and Q31 shown in FIG. 2. If, for example, the DC potential of the color-difference signal supplied to the transistor Q14 is a little higher than that of the color-difference signal supplied to the transistor Q18, the error .DELTA.VBE causes the level of normal signal waveforms which are as shown by full lines in FIGS. 4(c) and 4(d) to change to signal waveforms which are shown by dotted lines in FIGS. 4(c) and 4(d). As a result, modulation carrier components would be generated during the blanking periods A and B, as shown by dotted lines in FIGS. 4(g) and 4(h).
In a case where the image signal has no color component, a black-and-white image signal is reproduced by a reproducing apparatus having the circuit of FIG. 2 or, where there is no image signal itself, the above-stated phenomenon causes such a color component that should not be generated to appear on a monitor device which is connected to the reproducing apparatus having the circuit of FIG. 2. Further, if the level of the color-difference signal supplied to the circuit described is low, the levels of balanced-modulated color-difference components would vary to cause changes in the hues of the original color components.
As a result of the recent trend of microminiaturizing integrated circuits, it has become extremely difficult to reduce the error .DELTA.VBE which is resulting from the positional deviation of a mask pattern in arranging the circuit described above in the form of an integrated circuit. This difficulty has caused either the color encoder to be discretely arranged, instead of arranging it in the form of an integrated circuit, or an additional circuit to be arranged outside of the color encoder to compensate for any leakage in the modulation carrier component resulting from the above-stated error .DELTA.VBE.